1. Field of the Invention
The present invention relates to an algorithm and system that reduces the audible motor noise induced by the single current shunt feedback topology of conventional PWM inverter drives.
2. Related Art
FIG. 1 a shows the Space Vector Plane of a 2-level inverter. In order to observe dc link current and allow reliable current sampling, a minimum pulse width constraint (FIG. 1b) has to be imposed whenever the voltage vector enters the shaded regions (Sector Crossings) in FIG. 1a. Examples of these techniques are described in the above-mentioned U.S. Pat. No. 7,102,327; in Ser. No. 10/402,107; and in Blaabjerg et al., “Single Current Sensor Technique in the DC-link of Three-phase PWM-VS Inverters-A Review and the Ultimate Solution,” IEEE, pages 1192-1202 (1996), incorporated by reference and therefore will not be described further herein.
In a 2-level inverter system, the instantaneous current waveform in the dc link is composed of current pulses. The current pulse width is reduced as the modulation index (motor speed) decreases; up to a point where the minimum pulse width constraint (hardware dependent, typically 0.5 to 2 usec) has to be imposed in order to acquire reliable current feedback data. As a consequence of applying this minimum pulse width constraint, the current harmonics increase. The audible motor noise spectrum also increases and spreads out, especially at low motor speeds (say less than 20 percent of rated speed), where the voltage vector of FIG. 1a spends a longer duration in the shaded area. This leads to unacceptable noise performance in some applications.